1. Field of the Invention
The present invention relates generally to gate arrays, and more particularly, to an arrangement of logic cell regions and interconnection regions for such arrays.
2. Description of the Background Art
A gate array comprises gates referred to as basic cells arranged orderly and regularly (in an array manner) on an LSI (large-scale integrated circuit) chip. The gate array is an LSI designed by significantly standardizing designing, developing and manufacturing processes of a custom LSI to make the most of the CAD (computer aided design) and manufactured by means in a semi-custom manner. In the gate array, the developing period and the manufacturing cost can be reduced, although the chip size is increased, as compared with a full-custom LSI. Thus, the gate array has been improved and developed for higher performance and a higher function since the gate array was put into practice in the early 1970's.
Following are approaches for enhancing performance, particularly, increasing integration density of the gate array:
(a) pattern miniaturization
(b) improvement of chip architecture (method for arranging basic cells and method for arranging interconnection regions)
(a) Miniaturization is conventionally used as a means for increasing integration density of the LSI including a dynamic memory and hence, the detailed description thereof is omitted.
(b) Chip architecture is an item peculiar to the gate array. Taking a CMOS (complementary metal oxide semiconductor) gate array as a concrete example, the following are principal methods of chip architecture improvement:
(b-1) gate isolation PA1 (b-2) carpeting gate array PA1 (b-1) Gate isolation is related to a transistor isolating method. FIG. 1A is a plan view showing an isolated state of each gate to occur when employing a field oxide film method which is the most general transistor isolating method, and FIG. 1B is a cross sectional view showing a portion taken along a line IB--IB in FIG. 1A. Referring to FIGS. 1A and 1B, a conventional gate array using a field oxide film comprises a field oxide film 31 for isolating transistors, P type source-drain regions 2, N type source-drain regions 3, gates 4 of MOS transistors, a V.sub.DD line 5, a GND power-supply line 6, P channel transistor 7 and N channel transistors 8. A basic cell serving as an element in assembling system circuits comprises two sets of P channel transistors and N channel transistors. Since the transistors are isolated by the field oxide film 31, this field oxide film method has the following disadvantages:
(a) Since two sets of P channel transistors and N channel transistors constitute a basic cell, the size of the basic cell is fixed.
(b) As shown in FIG. 1B, peripheral portions 33 of the field oxide film 31 formed by LOCOS extends to the active regions. These portions are called bird's beaks. Since bird's beaks 33 appear in both ends of the field oxide film 31, the distance between cells is increased.
In order to overcome this disadvantage, the gate isolation was invented. The gate isolation is a method in which transistors respectively having channels of the same conductivity type are not isolated by the field oxide film. FIG. 2A is a plan view showing a gate array subjected to gate isolation, and FIG. 2B is a cross sectional view showing a portion taken along a line IIB--IIB in FIG. 2A. As shown in FIGS. 2A and 2B, a P type source-drain diffusion region 2 and an N type source-drain diffusion region 3 are formed in a stripe shape without a field oxide film. Thus, the transistors are structured in a column (array) manner. A basic cell 9 in the gate isolation method comprises one set of P channel transistor and N channel transistor, as represented by a dotted line in FIG. 2A. Isolation between the transistors is achieved by fixing a gate 4 at a V.sub.DD level by a gate contact 10 in the P channel transistor while fixing a gate 4 at a GND level by a gate contact 10' in the N channel transistor. In this method, integration is improved, as compared with the oxide film isolating method. This method is described in an article by I. Ohkura, entitled "Gate Isolation-A Novel Basic Cell Configuration for CMOS Gate Array", CICC 82, 1982, pp. 307-310.
Hereinafter, the direction of the X-axis (in which channels of the same conductivity type are continuously arranged) in FIG. 2A is referred to as a channel length direction of the basic cell, and the direction of the Y-axis (in which gates are continuously arranged) is referred to as a channel width direction of the basic cell.
(b-2) Carpeting is considered as a second generation of the gate array. FIG. 3 is a diagram of a master chip in a conventional gate array. In FIG. 3, the conventional gate array comprises basic cell columns 11 each having basic cells 9 arranged therein, field oxide films 12 each used as an interconnection channel region between logic cells, and input/output buffer and pad regions 14. The width of each of the field oxide films 12 each used as an interconnection channel region is set to a width in which several and several tens of interconnection tracks can be laid out such that a desired circuit can be laid out by the CAD. A carpeting gate array (referred to as SOG-Sea of Gate hereinafter) was invented for effective arrangement and interconnection in the gate array. FIG. 4 is a plan view of the SOG. In FIG. 4, basic cell columns 11 are carpeted also in a region where the field oxide films 12 exist in FIG. 3. Portions other than the region are the same as those in FIG. 3. The details thereof are described in an article by H. Fukuda, entitled "A CMOS Pair-Transistor Array Masterslice", Digest of VLSI Symposium 82, 1982, pp. 16-17.
As shown in FIG. 4, a semiconductor substrate having a plurality of PMOS transistors and NMOS transistors formed therein is referred to as a master chip.
FIG. 5A is a symbol showing a 3 input NAND circuit, and FIG. 5B is a diagram showing an equivalent circuit of the 3 input NAND circuit. Reference numerals in FIG. 5B correspond to reference numerals in FIG. 6A. FIG. 6A is a plan view showing the 3 input NAND circuit shown in FIG. 5B formed on a gate array. FIG. 6B is a cross sectional view showing a portion taken along a line VIB--VIB in FIG. 6A, and FIG. 6C is a cross sectional view showing a portion taken along a line VI--VI in FIG. 6A. Referring to FIGS. 6A, 6B and 6C, the 3 input NAND circuit is formed on regions isolated by isolating gates 15 on a logic cell column 20.
In FIG. 6A, the 3 input NAND circuit comprises three N channel MOS transistors 53A, 53B and 53C connected in series and P channel MOS transistors 56A, 56B and 56C connected in parallel. The three P channel MOS transistors 56A, 56B and 56C connected in parallel are connected to a V.sub.DD line 5 through contacts 54A and 54B. The three N channel MOS transistors 53A, 53B and 53C connected in series are connected to a GND line 6 through a contact 19. An input signal A (see FIGS. 5A and 5B) is applied to gates of the N channel MOS transistor 53A and the P channel MOS transistor 56A through interconnections 51A, 52A and 58A. Similarly, an input signal B is applied to gates of the N channel MOS transistor 53B and the P channel MOS transistor 56B through interconnections 51B and 52B. An input signal C is applied to gates of the N channel MOS transistor 53C and the P channel MOS transistor 56C through interconnections 51C and 52C.
A source region of the N channel MOS transistor 53A is connected to output signal lines 59 and 60 through a contact 55 and an interconnection 57, as shown in FIG. 6A. Drain regions 2 of the three P channel MOS transistors 56A, 56B and 56C are connected to the output signal lines 59 and 60 through the contact 54B, an interconnection 62 and the interconnection 57. In FIG. 6A, interconnections on a first layer are represented by dots, and interconnections on a second layer are represented by oblique lines.
In FIG. 6A, a basic cell column 9 is used as a logic cell column 20 for assembling circuits or interconnection channel regions 21 for interconnections between logic cells.
Meanwhile, in the conventional gate array shown in FIG. 3, the number of tracks to be interconnected which can be provided in each of the interconnection channel regions 12 on the oxide film is fixed to, for example, 30. However, the respective numbers of tracks to be interconnected in all channels need not be necessarily the same. Thus, in order to utilize the basic cell column as a logic cell, the number of tracks to be interconnected must be less than the number of tracks provided in the interconnection channel region.
FIG. 7A is a plan view showing an actual layout pattern of the SOG comprising the logic circuit as shown in FIG. 6A which is viewed in a macro manner. A portion where right and downward oblique lines are drawn represents a logic cell region 13, a square symbol 18 represents a through hole between metal interconnections, a straight line 16 parallel to the direction of the X-axis represents a first metal interconnection layer, and a straight line 17 parallel to the direction of the Y-axis represents a second metal interconnection layer. A plurality of basic cell columns out of the basic cell columns 11 as carpeted are respectively used as logic cell columns 20, and basic cells 9 in the basic cell columns used as the logic cell columns are respectively used as logic cells. The basic cell columns 11 which exist above and below each of the logic cell columns 20 are respectively used as interconnection channel regions 21 in order to ensure the number of tracks required for interconnections between the logic cells. Thus, in the SOG, the degree of freedom for the layout by the CAD is increased. Therefore, as compared with the gate array shown in FIG. 3, integration is improved. However, if there is one track to be interconnected which cannot be contained in a interconnection channel region in one column, another interconnection channel region 21 is required for the one track to be interconnected. Thus, there remains a useless interconnection region.
In order to overcome this disadvantage, a method has been devised for decreasing the length in the channel width direction of each of the basic cell columns. In the SOG, the above described basic cell columns 11 are respectively used as the interconnection channel regions 21. Thus, if the number of tracks to be interconnected for each basic cell column is 30, each of the interconnection channel regions can be changed every 30 tracks (which is referred to as track pitch 30 hereinafter). For example, if 32 tracks to be interconnected are required in a given interconnection channel region 21, two basic cell columns 11 are utilized as the interconnection channel region 21. However, the efficiency of the use of tracks is very low, i.e., 32/60. If the number of tracks for each basic cell column is decreased from 30 to 20, the track pitch is decreased to 20, so that the efficiency of the use of tracks is improved to be 32/40.
Even if such a method has been revised, there is still useless interconnection regions. The background of generation of such useless regions will be described briefly in the following.
FIG. 7B is an enlarged view of a basic cell 9 constituting the SOG shown in FIG. 7A. Generally, the length and width of one basic cell are determined, one such example shown in FIG. 7B. Referring to FIG. 7B, the length and width of a conventional basic cell are about 50 .mu. and about 5 .mu., respectively. In this manner, the ratio of the length and width of the basic cell (hereinafter referred to as a aspect ratio) has been determined in general, which was about 10:1 to 5:1. The said dimension is defined by the dimension of two transistors constituting the basic cell. More specifically, a prescribed gate width is necessary to provide a prescribed driving power of the transistor and, in addition, prescribed dimensions of the source drain regions are necessary. Under such conditions, the length of a portion corresponding to the gate width of the basic cell (the dimension represented by l in FIG. 7B) cannot be freely changed.
Referring to FIGS. 7B and 7C, the reason why an interconnection layer 17 has been provided for every 1 basic cell will be described. In FIG. 7C, the interconnection layer 17 is shown in the same scale as in FIG. 7B. Referring to FIG. 7C, the width of the interconnection layer 17 is about 2 .mu. and the pitch is about 3.5 .mu.. Accordingly, referring to FIGS. 7B and 7C, one interconnection layer 17 is provided approximately on one basic cell.
In the above described gate array, SOG and standard cell, a system is configured by combining required logic cells from several hundred types of groups of circuits (cell libraries) as previously assembled. Thus, in logic cells entered into the cell libraries, interconnections between transistors in the logic cells have been already accomplished. Thus, when a chip (system) is configured, interconnections are only provided between the logic cells. In arrangement and interconnection, it is desirable to completely isolate interconnection regions in the logic cells from interconnection regions between logic cells. Poly-cell is an effective method for making the heights of the logic cells approximately constant. Thus, regions suitable for the interconnections between the transistors in the logic cells are required. As a result, the height of a column of the MOS transistors, i.e., the channel width of the transistors cannot be decreased without any restriction, so that the channel width of at least 4 to 5 tracks is required.
FIG. 8 is an enlarged plan-view of a portion encircled by VIII in FIG. 4. Referring to FIG. 8, in the conventional improved carpeting gate array, through holes 73 each serving as an input/output of a logic cell may be interconnected as shown. On this occasion, second metal interconnection layers 17 are arranged as shown since it must be taken out in interconnection channel regions 21. Consequently, interconnections in a portion represented by A are close to each other, so that it is difficult to provide another interconnection in this region. In this case, when a through hole 71 on one logic cell column 20A and a through hole 72 on the other logic cell column 20B must be interconnected with each other, for example, a straight interconnection cannot be provided from the through hole 71 to the through hole 72, so that the interconnection must be bypassed as represented by 74.